Fpga Implementation of 3gpp-lte Physical Downlink Control Channel Using Diversity Techniques

Long Term Evolution (LTE) of UMTS Terrestrial Radio Access and Radio Access Network is a Fourth Generation wireless broadband technology which is capable of providing backward compatibility with 2G (Second Generation) and 3G (Third Generation) technologies. LTE is able to deliver high data rate and low latency with reduced cost This paper proposes a novel architecture for Single Input Single Output(SISO) 1x1, Multiple Input Single Output (MISO) 4x1, Multiple Input Multiple Output (MIMO)4x2 for Physical Downlink Control Channels of LTE. The physical downlink channel processing involves as scrambling, modulation, layer mapping, precoding, data mapping to resource elements at transmitter and demapping from resource elements, decoding, delayer mapping, demodulation and descrambling at receiver. In the proposed architecture, these steps are carried out in a single architecture comprises of all the data and control channels. Based on simulation and implementation, results are discussed in terms of Register Transfer Level (RTL) design, Field Programmable Gate Arrays (FPGA) editor, power estimation and resource estimation. To simulate all the modules of all control channels, ModelSim is used. For synthesis and implementation of the above architecture PlanAhead 13.2 tool on Virtex-5, xc5vlx50tff1136-1 device board is used. KeywordsLong Term Evolution (LTE), Single Input Single Output (SISO), Multiple Input Single Output (MISO), Multiple Input Multiple Output (MIMO) Physical Downlink Shared Channel (PDSCH), Physical Broadcast Channel (PBCH) and Physical Multicast Channel (PMCH).